We used Synthagate for a lot of designs – processors, robots, controllers etc. On our site you will find four designs for demonstration of our HLS and RTL tool Synthagate – Codec, Light, ALBI, Washroom and Nonsense. Each one was designed three times beginning from:
- GUI AsmCreator;
- ASMs in System C;
- ASMs in VHDL.
In the process of design Synthagate automatically constructs many folders corresponding to each stage of design. The design of any system contains 15 folders and each folder contains a lot of design documentation. Here we left 9 folders, it is enough for understanding of the design steps.
Design begins from two folders - Initial and Components.
1. Folder Initial contains:
- .asd files of ASMs, if a designer begins from GUI;
- .cpp files of ASMs, if a designer begins from SystemC;
- .vhd files of ASMs, if a designer begins from VHDL.
Once again, cpp and vhd files do not contain a design in System C or VHDL, but only ASMs in these languages. The different representation of ASMs are here. A designer shouldn't think about minimisation of initial ASMs, Synthagate will do that.
If a designer begins from ASM Creator (we strongly advise that) he must use the button build to get internal representation of ASM in three files gsa, mic and txt. If the designer prefers to use SystemC or VHDL, he should prepare ASMs in cpp or vhd files which be automatically transformed into internal files gsa, mic and txt. If the design contains generalized operators (subASMs), they must be in folder General which is a subfolder of folder Initial.
2. Here we gave only several – one for the beginning of design (folders Initial and Spec), one for High level synthesis (folder HLS), one for RTL design (folder RTL) and one for Logic design of Control Unit (folder ControlUnitLogic). File HLSTotalTime.tim contains the total time of automatic design from initial ASM descriptions till design of Control unit in folder ControlUnitLogic. Synthagate automatically constructs specifications in folder Spec in dialog with a designer. Here we constructed them before the designs. Summary of all folders:
- Files Funcmi.vhd and my_package.vhd (funcmi.cpp and funcmi.h) in Folder HLS are the result of High level synthesis. Funcmi.vhd (Funcmi.cpp) presents the behavior of the whole designed system as some virtual FSM. If you have the test bench for the simulation at this high level, you can use the same test bench for simulation at the RTL level in folder RTL. The designer can simulate the design with the VHDL file (funcmi.vhd) or with the System C file (funcmi.cpp)
- Folder RTL, as other folders, was constructed automatically. It contains:
- Components of Data path in VHDL;
- Dp.vhd– Data path in VHDL;
- Structm.vhd– Control unit in VHDL;
- Top.vhd– the upper level of the design as a composition of Data path and Control Unit.