Are High Level Synthesis tools good or bad?

With big interest I followed and even took part in a very lively discussion “Numbers don’t lie: there is virtually no interest in high level synthesis”, opened by Matthieu Wipliez which is CTO and co-founder of the Synflow EDA start-up company.

The main topic of this discussion was who should make a design with HLS tools – a SW specialist (designer of algorithms) or a HW specialist. I am sure that both should do design together from the beginning. Only in such a case, the HW specialist will avoid mistakes from not understanding how the hardware must work and, at the same time, the HW specialist will understand better the algorithms which should be implemented in the designed system. Unfortunately, nobody said exactly why HLS good or bad in that discussion.

I looked carefully at the critical papers about HLS for the last two years and wrote here some remarks from these papers. It is not my own remarks. Maybe designers of HLS tools or some specialists using HLS will confirm or disclaim these remarks with corresponding examples.

  1. The handwork is necessary at the transition from high level to RTL;
  2. The existing HLS tools are useful only for special types of the design systems, mainly for data path dominated systems.
  3. There are some problems with timing and the designer should fix them by hand;
  4. Connections between elements of Data path (buses or direct connections) should be defined at the high level;
  5. Splitting of registers should be defined at the high level;
  6. Design of FSM (Control unit) requires manual rework at RTL;
  7. Difficult to use IP cores automatically at the high level and RTL;
  8. Test benches used for simulation at the high level cannot be used at RTL without manual rework;
  9. Specifications at RTL needs handwork;
  10. If a designer must change something after simulation at RTL (the design is correct but there are problems with speed, area or power), it is difficult to come back to the high level to improve the design;
  11. In the case of problems mentioned in point 10, a designer can fix them only at RTL;
  12. It is difficult to master a design methodology of HLS for HW designers;
  13. A designer gets better designs beginning from RTL;
  14. It is difficult to understand a design at RTL constructed automatically from the high level.

I ask the people from industry or academy to give examples of designs made with HLS. Last time when I was at the presentation of Vivado, a guy from Xilinx demonstrated design of the system summarizing two matrices. Please, give examples of designs with not trivial control units.

Now about “Numbers don’t lie”:

  1. The group Electronic System Level – ESL contains not 69 members but 2085 including myself;
  2. Argument about 29 years to HLS isn’t correct. Exactly 29 years ago VHDL and Verilog appeared and it was a revolution in the design of that time chips containing not more than 100 thousand gates. There was no need in HLS which did not yet exist. There were only some programs supporting some academic researches.