- Contents
- 1. FSMs
- 2. Logic circuits

These benchmarks are the result of collection of examples over the past years from different sources. This section has two subsections – *FSM* and *Logic Circuits* (combinational circuits). Subsection *FSM* contains five sets according to the complexity of examples – *Small*, *Medium*,* Large*, *Huge* and *SuperHuge*. Subsection *Logic Circuits *contains four sets – *Small*, *Medium*, *Large* and *Huge**.*

*You can download these benchmarks.*

Each set in the* subsection FSMs* has four folders:

- ASMs (Algorithmic State Machines).
- T1- FSM as a table;
- VHDL – FSM in VHDL;
- Verilog – FSM in Verilog.

To understand the ASM representation see Figure 1.

**Figure 1. ASM with numbered vertices**

ASM is the directed connected graph containing an initial vertex (Begin), a final vertex (End) and a finite set of operator and conditional vertices. In ASM, a logical condition is written in each conditional vertex. An operator (microinstruction), containing zero, one, two or more microoperations, is written in each operator vertex of ASM. Microoperations written in the same operator are implemented simultaneously. We numbered vertices of ASM in Fig. 1 by underlined numbers from 0 to 19.

Each ASM is presented with two files – *name.gsa *(Fig. 2)* *and* name.mic *(Fig. 3). File *name.gsa *is two connected list of ASM graph. Each row of this list corresponds to one vertex. Columns in this list:

- The number of the vertex;
- The content of the vertex –
*Y*for operator and_{n}*x*for logical condition;_{m} - The number of the vertex following the operator vertex or output ”1” of the conditional vertex;
- The number of the vertex following output “0” of the conditional vertex. Vertices
*Begin*and*End*are described as operator vertices. The maximal number of vertex (*19*in our example) is at the top of this file on the left.

**Figure 2. File name.gsa (ASM as two-connected list)**

File *name.mic *contains the list of operators with their microoperations.

Y0

**Y1 y1 y2**

**Y2 y4**

**Y3 y5 y6 y7**

**Y4 y8 y9**

**Y5 y1 y3**

**Y6 y6 y7**

**Y7 y3 y4**

**Y8 y3 y6 y10**

**Figure 3. File name.mic (Operators and microoperations)**

Subsection *Logic Circuits *contains non-minimized combinational circuits. Each set in this subsection has five folders:

- M2 – netlists in files
*name.m12*. In such a file:

- numbers of gates are in the first column;
- inputs of gates (
*x*– input of circuit,_{i}*e*– output of gate_{p}*p*) are in the second column; - outputs of gates are in the third column.

- VHDL – logic circuits in VHDL;
- Verilog – logic circuits inVerilog;
- Edif – logic circuits in Edif;
- Blif – logic circuits in Berkeley format Blif.