In this Section we will shortly present the comparison results in the synthesis of Finite state machines and combinational circuits between Synthagate and tools from Synopsys, Mentor Graphics and ABC tool from Berkeley. Anyone can repeat these experiments by downloading the examples from our website. However, not all of these experiments were carried out during the last year. We would be grateful if someone sent us the new results.

Table 1 and Table 2 contains 5 columns. The name of the group (Small, Medium, Large, Huge) are in the first column. The next four columns contain the results of area optimization by Synthagate, ABC Berkelay, Precision and Quartus.

Table 1. Comparisons for FSMs (FPGA, 4-input Luts)


Table 2. Comparisons for Combinational circuits (FPGA, 4-input Luts)


 Tables 3 and 4 contain the results of comparisons in design FSMs and Combinational circuits with NOR – NAND gates from the library Class (Synopsys) between Synthagate and Synopsys.

Table 3. Comparisons with Synopsys for FSMs (ASIC, library Class)


*Here we gave comparisons for only six Huge examples since Synopsys could not design the biggest one from this group.

Table4. Comparisons with Synopsys for Combinational circuits (ASIC, library Class)


Design of Synthagate is 10–20 times faster vs. other tools.