Example is not the main thing in influencing others, it’s the only thing.
We used Synthagate for a lot of designs – processors, robots, controllers etc. On our site you will find four designs using Synthagate – Codec, SortMax, Nonsense and Washroom. Each one was designed twice beginning from:
- GUI AsmCreator;
- ASMs in System C.
You can download these examples here.
- Codec demonstrates a combination of Encoder and Decoder. First, uncompressed data is writing into memory M1. Encoder reads this data from memory M1, compresses it and writes this compressed data into memory M2. Then decoder reads compressed data from memory M2, decompresses it and writes decoded data into memory M3.
- To check the possibility of automatic design of very complex digital systems we gathered very different modes (operations) from various designs – robots, controllers, processors, communication devices etc. in one heap. Of course, nobody would like to implement such a wide variety of applications in one design. It is the reason we called this design Nonsense. Nevertheless, the design passes the same stages, the result of high level synthesis is in folder HLS (file Funcmi.vhd or Funcmi.cpp), the result of RTL design – in folder RTL and the result of Control unit synthesis with FPGA (area and delay optimizations with simulation for both cases) – in folder ControlUnitLogic. The time of design is 41.01 sec beginning from GUI and 43.60 sec beginning from ASMs in System C.
- Washroom is the design-joke of a virtual robot which goes to the washroom instead of us. We hope that we should never use such a robot. It is interesting that this design passes exactly through the same stages although it is a pure controller – its data path is empty.
In the process of design Synthagate automatically constructs many folders corresponding to each stage of design. Here we gave only several – one for the beginning of design (folders Initial and Spec), one for High level synthesis (folder HLS), one for RTL design (folder RTL) and one for Logic design of Control Unit (folder ControlUnitLogic). File HLSTotalTime.tim contains the total time of automatic design from initial ASM descriptions till design of Control unit in folder ControlUnitLogic. Synthagate automatically constructs specifications in folder Spec in dialog with a designer. Here we constructed them before the designs. Summary of all folders:
- Folder Initial contains asd files of modes (instructions) constructed by the designer beginning with GUI, or cpp files beginning from SystemC. For each asd file he must use the button build to get files gsa, mic and txt. If the designer prefers to use SystemC, he should prepare cpp files which be automatically transfered into internal files gsa, mic and txt. Folder General in the Initial folder contains the same files for generalized operators (subASMs).
- Files Funcmi.vhd and my_package.vhd (funcmi.cpp and funcmi.h) in Folder HLS are the result of High level synthesis. Funcmi.vhd (Funcmi.cpp) presents the behavior of the whole designed system as some virtual FSM. If you have the test bench for the simulation at this high level, you can use the same test bench for simulation at the RTL level in folder RTL. The designer can simulate the design with the VHDL file (funcmi.vhd) or with the System C file (funcmi.cpp)
- Folder RTL, as other folders, was constructed automatically. It contains:
- Components of Data path in VHDL;
- Dp.vhd– Data path in VHDL;
- Structm.vhd– Control unit in VHDL;
- Top.vhd– the upper level of the design as a composition of Data path and Control Unit.
- Folder ControlUnitLogic contains the design of the Control unit with FPGA (area optimization) and the same in subfolder DelayOpt – delay optimization. The report of the design is in the Excel file csv. This file includes:
- total is the number of luts in the Control Unit circuit. In these examples, we used luts with not more than 4-inputs, although it is possible to use luts with any number of inputs;
- avg is the average number of inputs in all luts;
- delay is the number of luts at the critical path of FPGA circuit (the delay of the circuit);
- elapsedtime is the design time of the circuit (min:sec).
Other files in Folder ControlUnitLogic:
- Files Structm_mkh.t1 and Structm_mkh.t12 are FSMs without state assignment and with one-hot state assignment.
- Files Structm_mkh.v and Structm_mkh.vhd are FSMs in Verilog and VHDL.
- Gate netlist is in the file Structm_mkh.g16. In this file: a) numbers of gates are in the first column; b) inputs of gates are in the second column; c) outputs of gates are in the third column. For example, the line “3 AND t52 x1 x5 d2 y7″ means that AND gate number 3 has three inputs – t52 (feedback from d_ff number 52), x1 and x5. The output of this gate goes to the output of circuit (y7) and to the input of d_ff number 2 (d2).
- File Structm_mkh.g17 is the same netlist with one additional second column. For example, the line “178 3 OR e85 e122 e127 e164 y73″ means that there are a maximum of three gates between the input of circuit and OR gate number 178. Its inputs are the outputs of gates 85, 122, 127 and 164.
- Files Structm_mkh.m96 and Structm_mkh.m97 are similar to Structm_mkh.g16 and Structm_mkh.g17, but the elements of these netlists are luts.
- File Structm_mkhr96_test.log is the result of simulation. During this simulation, our tool checks that the FPGA logic circuit (Structm_mkh.m96) really implements FSM Structm_mkh.t12, which is a model for the Control unit of the design system.