With big interest I followed and even took part in a very lively discussion “Numbers don’t lie: there is virtually no interest in high level synthesis”, opened by Matthieu Wipliez which is CTO and co-founder of the Synflow EDA start-up company.
The main topic of this discussion was who should make a design with HLS tools – a SW specialist (designer of algorithms) or a HW specialist. I am sure that both should do design together from the beginning. Only in such a case, the HW specialist will avoid mistakes from not understanding how the hardware must work and, at the same time, the HW specialist will understand better the algorithms which should be implemented in the designed system. Unfortunately, nobody said exactly why HLS good or bad in that discussion.
I looked carefully at the critical papers about HLS for the last two years and wrote here some remarks from these papers. It is not my own remarks. Maybe designers of HLS tools or some specialists using HLS will confirm or disclaim these remarks with corresponding examples.
- The handwork is necessary at the transition from high level to RTL;
- The existing HLS tools are useful only for special types of the design systems, mainly for data path dominated systems.
- There are some problems with timing and the designer should fix them by hand;
- Connections between elements of Data path (buses or direct connections) should be defined at the high level;
- Splitting of registers should be defined at the high level;
- Design of FSM (Control unit) requires manual rework at RTL;
- Difficult to use IP cores automatically at the high level and RTL;
- Test benches used for simulation at the high level cannot be used at RTL without manual rework;
- Specifications at RTL needs handwork;
- If a designer must change something after simulation at RTL (the design is correct but there are problems with speed, area or power), it is difficult to come back to the high level to improve the design;
- In the case of problems mentioned in point 10, a designer can fix them only at RTL;
- It is difficult to master a design methodology of HLS for HW designers;
- A designer gets better designs beginning from RTL;
- It is difficult to understand a design at RTL constructed automatically from the high level.
I ask the people from industry or academy to give examples of designs made with HLS. Last time when I was at the presentation of Vivado, a guy from Xilinx demonstrated design of the system summarizing two matrices. Please, give examples of designs with not trivial control units.
Now about “Numbers don’t lie”:
- The group Electronic System Level – ESL contains not 69 members but 2085 including myself;
- Argument about 29 years to HLS isn’t correct. Exactly 29 years ago VHDL and Verilog appeared and it was a revolution in the design of that time chips containing not more than 100 thousand gates. There was no need in HLS which did not yet exist. There were only some programs supporting some academic researches.
“It is not best that we should all think alike; it is a difference of opinion that makes horse races.”
Synthagate is the true 4th generation High Level Synthesis (HLS) tool that shortens the time-to-market by at least the factor of 3x practically for any applications. It performs the full automatic synthesis of digital systems from behavioral specification to HDL description at the Register Transfer Level (RTL). This tool allows to quickly implement, check and estimate multiple design versions, to find an optimized solution to the design problems, to produce automatically the design documentation and to simplify the digital system verification problems. The High Level Synthesis, implemented in Synthagate, is oriented to the design of the Control and Data Path Intensive Systems with very complex control units containing a lot of inputs and outputs.
Design Flow in Synthagate
The design flow in Synthagate is presented in Fig. 1. Algorithmic state machines (ASMs) are used in Synthagate as an input to describe the behavior of digital system – http://synthezza.com/how-does-synthagate-work/2/ . ASMs can be presented:
- As a graph, drawn with GUI (ASM Creator) – the special Synthagate graphical editor;
- As a text in pseudo code of System C.
Transformations of ASMs
ASM models and their transformations (http://synthezza.com/how-does-synthagate-work/4/) are used in Synthagate at all stages of behavior (TLM) and structural (RTL) synthesis. Synthagate is the only tool that implements various transformations of initial behaviors:
- ASM minimization. A designer shouldn’t think about minimization of an initial description – Synthagate automatically minimizes the number of vertices in the ASM graph.
- ASM combining. If a digital system behavior is rather complex but contains several modes (instructions), Synthagate will combine them into one ASM with minimization of operator and conditional vertices. There are no constraints on the number of separate ASMs to combine.
- Sub ASM insertion. At the last step of ASM transformations Synthagate inserts all component ASMs (generalized operators) and constructs one combined and minimized Functional ASM without generalized operators. This ASM presents a whole behavior of the design system.
The same steps take place when a designer initially presents ASMs in System C.
Functional Specifications. To design the behavior (TLM) description of a digital system the designer should not define each port or signal. Synthagate creates an XML code of the functional specification and the designer should only insert the length of several ports and signals (not all, only a very small part of them) in the dialog mode Funcmi.spec.
Behavior description of the design system. With Functional ASM Funcmi and the functional specification Funcmi.spec as an input, Synthagate automatically constructs the behavior description of the whole design system – a virtual FSM Funcmi.vhd in VHDL or Funcmi.cpp in System C.
After preparing the test bench at the behavior level the designer can simulate the functional project with any simulation tool. The same test bench can be used later at the last stage of design – after top design at the structural (RTL) level. For simulation at the High Level the designer can choose Funcmi.vhd or Funcmi.cpp.
Data Path design
External specifications. In Data path design Synthagate uses external specification ExtSpec.xml in XML constructed automatically.
Automatic generation of components. Synthagate automatically generates VHDL codes for components of Data Path. If a designer would like to use some predesigned IP cores, he must put their RTL codes in folder Components before the design. Later these components will be included in the library of automatically generated units. In our examples we used core memory from Altera Ram65536x8.vhd.
Generation VHDL code for Data Path. At the last step of Data Path design Synthagate automatically instantiates components in the Data Path Dp.vhd.
Control Unit design
Synthagate automatically creates the RTL code of Control unit Structm.vhd. Its input signals are feedbacks from the Data path and some input signals of the digital system, its outputs are micro operations implemented in the Data path and some output signals of the digital system.
At the last stage, Synthagate creates the code for the top level automatically by instantiating Control Unit and Data Path into Top.vhd.
What makes Synthagate different?
- Synthagate does not require learning a new design language. In two to three days, a designer can begin to use Synthagate to describe design system behaviors at the high level of representation.
- Synthagate is the only HLS tool to design Control Intensive and Data Path Systems with very complex Control Units containing numerous inputs and outputs. It works with hierarchical designs at the functional and structural levels.
- Synthagate is the only tool to implement various transformations of initial behavior – Algorithmic State Machines.
- Synthagate automatically minimizes the number of vertices in initial ASMs, which reduces chip area. The designer does not need to think about the minimization of the initial behaviors.
- Synthagate uses ASMs at all stages of HLS and automatically constructs all functional and structural specifications.
- Using different generalized operators (subASMs), a designer can quickly design and check different architectures by time and/or area.
- Synthagate automatically creates direct and indirect connections (buses) between units using procedures which optimize not only the Data path (its area and speed) but also the Control unit constructed at the following design stages.
- Synthagate simplifies the verification process for the System on Chip:
- Automatic correct-by-construction synthesis,
- Functional Verification (algorithmic level),
- Structural verification (RTL level),
- Automatic design of the skeleton of test bench for the Data path.
- Power saving: We know how automatically decompose Control Unit (FSM) and Data path and switch off “sleeping” components of these units to consume energy. It will be implemented in Synthagate soon.
- Synthagate provides the highest QoR, practically unlimited Capacity, record Speed of synthesis and removes most restrictions to users’ design skill sets.
- In most SoCs, a Control unit is an irregular multi-level and multi-output circuit in which delay of connectors between gates may be a lot more than a delay of gates themselves. Synthagate can construct optimized six-matrix regular FSM’s circuits while minimizing the area and increasing the speed. This is especially important for SoCs.
- Synthagate allows the immediate use of any IP cores designed by other companies.
- In the process of design Synthagate creates a lot of documents corresponding to each design stage. These documents can be used to prepare the project documentation. In the case of some designer’s mistakes at the initial stages of the project, these documents allow to return quickly to previous design stages and fix possible problems.
We used Synthagate for a lot of designs – processors, robots, controllers etc. On our site you will find four designs using Synthagate – Codec, SortMax, Nonsense and Washroom. Each one was designed twice beginning from:
- GUI AsmCreator;
- ASMs in System C.
You can download these examples here – http://synthezza.com/examples-of-hls/.
Synthagate fast Logic Synthesis of FSM and combinational circuits reduces the circuit area of very complex Finite state machines and combinational circuits by as much as 50%, compared with results obtained by the best industrial tools. At the same time, Synthagate runs faster than other tools by a factor of 10 or more (http://synthezza.com/logic-synthesis-in-synthagate-4/). We are going to present Synthagate Logic Synthesis for the special discussion.