Samary Baranov, Prof., PhD and Doct. Sc. has more than thirty years experience in the electronics industry. In 1975 he joined the Computer Engineering Dept. of the University of Precise Mechanics and Optics in St. Petersburg as a professor. Hundreds of his students, including about 80 with Masters Degrees and 20 with Ph.D. degrees, work successfully in Canada, Germany, Israel, Russia and the USA for well known IT companies, such as Apple, Intel, IBM, National Semiconductors, Motorola, etc.
In 1991, Samary Baranov joined the Dept. of Mathematics and Computer Science at the University of Beer-Sheva (Israel) as a professor and in 1994 he became a professor in the Computer Science Dept. and the Head of the Center for System-on-Chip Design at the Holon Institute of Technology (HIT). He lectured at the Electrical and Computer Engineering Dept. of University in Beer Sheva, Tel Aviv University, Bar Ilan University. At the same time he worked as a consultant for several high-tech companies in Israel. Now he is teaching main courses in the System-on-Chip Design in Bar Ilan University and Holon Institute of Technology.
In February 2001, he founded the North American Institute of Computer Systems (NAICS) in Toronto – the first training center in Canada to offer an advanced and intensive 250 hour post-graduate curriculum “Electronic Hardware Design” devoted to teaching Design Methodology, Hardware Description Languages (VHDL and Verilog), EDA Tools, ASIC and FPGA Design, Verification of Digital Systems etc. More than 250 students (bachelors, masters and PhDs) successfully finished this course in 2001 – 2003.
Prof. Baranov is the author of twelve books in Russian, French and English and more than 80 papers.
He has developed design methodology for High-Level Synthesis of digital systems and created EDA tool Synthagate (former Abelit) supporting this design methodology and implementing full automatic High Level Synthesis (HLS) of digital systems. Synthagate is the first true 4th generation HLS tool which shortens time-to-market for a complex SoC designs by the factor of 3x and allows very fast to implement, check and estimate many possible design versions, to find an optimized decision of the design problems and to simplify the verification problems for digital systems. Logic synthesis of Synthagate reduces the circuit area on the chip by as much as 20% – 50%, compared with results of the best USA industrial tools from Synopsys, Xilinx, Altera and Mentor Graphics and yet the run times of these other tools exceed that of Synthagate by more than a factor of 10.