Temp

-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram 
-- ============================================================
-- File Name: ram65536x8.vhd
-- Megafunction Name(s):
--    altsyncram
-- Simulation Library Files(s):
--    altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions 
--and other software and tools, and its AMPP partner logic 
--functions, and any output files from any of the foregoing 
--(including device programming or simulation files), and any 
--associated documentation or information are expressly subject 
--to the terms and conditions of the Altera Program License 
--Subscription Agreement, Altera MegaCore Function License 
--Agreement, or other applicable license agreement, including, 
--without limitation, that your use is for the sole purpose of 
--programming logic devices manufactured by Altera and sold by 
--Altera or its authorized distributors.  Please refer to the 
--applicable agreement for further details.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY altera_mf;
USE altera_mf.all;

ENTITY ram65536x8 IS
 PORT
 (
  address  : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
  clock  : IN STD_LOGIC  := '1';
  data  : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
  wren  : IN STD_LOGIC ;
  q  : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
 );
END ram65536x8;

ARCHITECTURE SYN OF ram65536x8 IS

 SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 COMPONENT altsyncram
 GENERIC (
  clock_enable_input_a  : STRING;
  clock_enable_output_a  : STRING;
  intended_device_family  : STRING;
  lpm_hint  : STRING;
  lpm_type  : STRING;
  numwords_a  : NATURAL;
  operation_mode  : STRING;
  outdata_aclr_a  : STRING;
  outdata_reg_a  : STRING;
  power_up_uninitialized  : STRING;
  read_during_write_mode_port_a  : STRING;
  widthad_a  : NATURAL;
  width_a  : NATURAL;
  width_byteena_a  : NATURAL
 );
 PORT (
   address_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
   clock0 : IN STD_LOGIC ;
   data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
   wren_a : IN STD_LOGIC ;
   q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
 );
 END COMPONENT;

BEGIN
 q    <= sub_wire0(7 DOWNTO 0);

 altsyncram_component : altsyncram
 GENERIC MAP (
  clock_enable_input_a => "BYPASS",
  clock_enable_output_a => "BYPASS",
  intended_device_family => "Cyclone IV GX",
  lpm_hint => "ENABLE_RUNTIME_MOD=NO",
  lpm_type => "altsyncram",
  numwords_a => 65536,
  operation_mode => "SINGLE_PORT",
  outdata_aclr_a => "NONE",
  outdata_reg_a => "CLOCK0",
  power_up_uninitialized => "FALSE",
  read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
  widthad_a => 16,
  width_a => 8,
  width_byteena_a => 1
 )
 PORT MAP (
  address_a => address,
  clock0 => clock,
  data_a => data,
  wren_a => wren,
  q_a => sub_wire0
 );

END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram65536x8.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram65536x8.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram65536x8.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram65536x8.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram65536x8_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_package.all;

entity Funcmi is
	port (
		bit0 : in std_logic;
		clk : in std_logic;
		codcomplete : out std_logic;
		decodcomplete : out std_logic;
		dma : in std_logic;
		ext_adr : in std_logic_vector(15 downto 0);
		ext_in : out std_logic_vector(7 downto 0);
		ext_out : in std_logic_vector(7 downto 0);
		ext_rdwr : in std_logic;
		idle : out std_logic;
		m : in std_logic;
		nelem : in std_logic_vector(15 downto 0);
		rst : in std_logic;
		rwrite2m2 : out std_logic_vector(15 downto 0);
		rwrite2m3 : out std_logic_vector(15 downto 0);
		s : in std_logic
	);
end Funcmi;

architecture ARC_Funcmi of Funcmi is

	type FSMStates is (
		a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, 
		a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, 
		a25, a26, a27, a28, a29, a30, a31, a32, a33, a34, a35, 
		a36, a37, a38, a39, a40, a41, a42, a43, a44, a45, a46, 
		a47, a48, a49, a50, a51, a52, a53, a54, a55, a56, a57, 
		a58, a59, a60, a61, a62, a63, a64, a65, a66, a67, a68, 
		a69, a70, a71, a72, a73, a74, a75, a76, a77, a78, a79, 
		a80, a81, a82, a83, a84, a85, a86, a87, a88, a89
	);
	type m1_type is array (integer range 0 to 65535) of std_logic_vector(7 downto 0);
	type m2_type is array (integer range 0 to 65535) of std_logic_vector(7 downto 0);
	type m3_type is array (integer range 0 to 65535) of std_logic_vector(7 downto 0);

	signal bitcnt : std_logic_vector(3 downto 0);
	signal br : std_logic_vector(7 downto 0);
	signal cnt : std_logic_vector(7 downto 0);
	signal cnt_elem : std_logic_vector(15 downto 0);
	signal cnt_m1_m3 : std_logic_vector(15 downto 0);
	signal cnt_m2 : std_logic_vector(15 downto 0);
	signal currentState : FSMStates;
	signal m1 : m1_type;
	signal m2 : m2_type;
	signal m3 : m3_type;
	signal mac1 : std_logic_vector(15 downto 0);
	signal mac2 : std_logic_vector(15 downto 0);
	signal rbyte : std_logic_vector(7 downto 0);
	signal rd : std_logic_vector(7 downto 0);
	signal relem : std_logic_vector(15 downto 0);
	signal rfilelength : std_logic_vector(15 downto 0);
	signal rlengthd : std_logic_vector(7 downto 0);
	signal rmask : std_logic_vector(7 downto 0);
	signal rmax : std_logic_vector(7 downto 0);
	signal rmin : std_logic_vector(7 downto 0);
	signal rt1 : std_logic_vector(7 downto 0);
	signal rt2 : std_logic_vector(7 downto 0);
	signal rtemp1 : std_logic_vector(15 downto 0);
	signal shcnt : std_logic_vector(7 downto 0);

begin
	process (clk , rst)

		variable m1_address : std_logic_vector(15 downto 0);
		variable m2_address : std_logic_vector(15 downto 0);
		variable m3_address : std_logic_vector(15 downto 0);

	procedure proc_Funcmi is 
	begin

	case currentState is
	when a1 =>
		if (s and dma and ext_rdwr) = '1' then
			m1_address := ext_adr;
			m1(to_integer(unsigned(m1_address))) <= ext_out;
			currentState <= a9;

		elsif (s and dma and not ext_rdwr and m) = '1' then
			m3_address := ext_adr;
			currentState <= a6;

		elsif (s and dma and not ext_rdwr and not m) = '1' then
			m2_address := ext_adr;
			currentState <= a8;

		elsif (s and not dma and bit0) = '1' then
			decodcomplete <= '0';
			currentState <= a4;

		elsif (s and not dma and not bit0) = '1' then
			relem <= nelem;
			codcomplete <= '0';
			currentState <= a3;

		else
			currentState <= a1;
			idle <= '1';

		end if;

	when a2 =>
		
			m2_address := mac2;
			m2(to_integer(unsigned(m2_address))) <= br;
			cnt_m2 <= std_logic_vector(unsigned(cnt_m2) + 1);
			currentState <= a15;

	when a3 =>
		
			mac2 <= (others => '0');
			br <= x"ff";
			cnt <= (others => '0');
			cnt_m2 <= (others => '0');
			currentState <= a2;

		.  .  .

	when a87 =>
		
			rd <= std_logic_vector(unsigned(rmax) - unsigned(rmin));
			currentState <= a34;

	when a88 =>
		if (rlengthd = x"00") then
			cnt_m1_m3 <= std_logic_vector(unsigned(cnt_m1_m3) - unsigned(relem));
			currentState <= a16;

		else
			shcnt <= (others => '0');
			mac1 <= rtemp1;
			rmask <= x"01";
			currentState <= a17;

		end if;

	when a89 =>
		
			bitcnt <= (others => '0');
			rbyte <= x"00";
			currentState <= a80;

	end case;
	end proc_Funcmi;

	begin
		if (rst = '1') then
			bitcnt <= (others => '0');
			br <= (others => '0');
			cnt <= (others => '0');
			cnt_elem <= (others => '0');
			cnt_m1_m3 <= (others => '0');
			cnt_m2 <= (others => '0');
			codcomplete <= '0';
			decodcomplete <= '0';
			ext_in <= (others => '0');
			idle <= '0';
			mac1 <= (others => '0');
			mac2 <= (others => '0');
			rbyte <= (others => '0');
			rd <= (others => '0');
			relem <= (others => '0');
			rfilelength <= (others => '0');
			rlengthd <= (others => '0');
			rmask <= (others => '0');
			rmax <= (others => '0');
			rmin <= (others => '0');
			rt1 <= (others => '0');
			rt2 <= (others => '0');
			rtemp1 <= (others => '0');
			rwrite2m2 <= (others => '0');
			rwrite2m3 <= (others => '0');
			shcnt <= (others => '0');
			for i in m1'range loop
				m1(i) <= (others => '0');
			end loop;
			for i in m2'range loop
				m2(i) <= (others => '0');
			end loop;
			for i in m3'range loop
				m3(i) <= (others => '0');
			end loop;

			currentState <= a1;
			idle <= '1';

		elsif (clk'event and clk = '1') then
			idle <= '0';
			proc_Funcmi;
		end if;
	end process;