The tremendous achievements in the chip technology allow the production of chips with hundreds of millions of gates. At the same time, the design technology of such circuits only slightly improved in the last ten years, especially at the highest system level. The traditional digital system design flow contains the manual creation of system description at RTL with Verilog or VHDL code. As a result, the time-to-market is increased three to four times for such complex digital chips. The only possibility to reduce a gap between future technological capability and lagging designer productivity is to raise the design from the current RTL to the algorithmic or behavior level and design new 4th generation HLS tools that can handle any types of digital systems.
High Level Synthesis (HLS), sometimes called Electronic System Level (ESL) or algorithmic or behavior synthesis, is the design process to convert the algorithmic behavior into hardware implementing this behavior.